1. Field of the Invention
The present invention relates to a receiver start-up compensation circuit, and more particularly, to a receiver start-up compensation circuit providing fast wake-up from a power-down mode.
2. Description of the Prior Art
Flat panel displays (FPD), characterized by light weight, low power consumption, and low radiation, are widely applied in portable electronic products such as notebook computers and personal digital assistants (PDAs). Therefore, it is necessary to design receivers for such displays in such a way so that the power consumption is as low as possible. For power-saving purpose, when an FPD has not received commands for a certain period of time, the receiver of the FPD begins to work in a power-down mode in which no current is being outputted. Upon receiving an activating signal from the FPD, the receiver leaves the power-down mode and enters a normal mode in which operational current is supplied to the FPD. The ability to quickly switch between the power-down mode and the normal mode is crucial to the performance of the FPD.
FIG. 1 shows a diagram of a prior art receiver circuit 10 of a display device. The receiver circuit 10 includes a reference current source Iref, a wake-up current source Im, and P-type metal oxide semiconductor (PMOS) transistors P1-P3. The PMOS transistors P1 and P2 form a current mirror circuit, in which the gates of the PMOS transistors P1 and P2 are coupled to each other at a node A of the receiver circuit 10, and the sources of the PMOS transistors P1 and P2 are coupled to a bias voltage VDD. The drain of the PMOS transistor P1 is coupled to the reference current source Iref. In order to generate a large output current Iout from a small current provided by the current source Iref, the size (W/L ratio) of the PMOS transistor P2 is usually larger than that of the PMOS transistor P1. Consequently, the capacitance C2 of the PMOS transistor P2 is larger than the capacitance C1 of the PMOS transistor P1. The drain current generated by “mirroring” the current supplied by the reference current source Iref using the PMOS transistor P1 to P2 is represented by Id. The PMOS transistor P3 has a source coupled to the drain of the PMOS transistor P2 at a node B of the receiver circuit 10, a drain coupled to a node C of the receiver circuit 10, and a gate coupled to a control voltage ENB. The wake-up current source Im is coupled between the bias voltage VDD and the node C of the receiver circuit 10.
When the receiver circuit 10 works in the power-down mode, the control voltage ENB is set to the bias voltage VDD, thereby turning off the PMOS transistor P3. The PMOS transistors P1 and P2 are turned on, and the voltage at the node B of the receiver circuit 10 is charged to VDD. The turned-off PMOS transistor P3 blocks the drain current Id of the PMOS transistor P2, and the output current Iout generated by the receiver circuit 10 in the power-down mode is near zero. For the receiver 10 to exit the power-down mode, the control voltage ENB is set to ground, thereby turning on the PMOS transistor P3 and pulling down the voltage at the node B to a voltage VB. The turned-on PMOS transistor P3 allows the drain current Id of the PMOS transistor P2 to pass, and the output current Iout generated by the receiver circuit 10 in the normal mode is equal to Id. The wake-up current source Im provides a small current for keeping the voltage of the node B of the receiver circuit 10 at a certain level, so that the receiver circuit 10 can switch faster between the power-down mode and the normal mode.
When the receiver circuit 10 exits the power-down mode, a voltage difference ΔVB is generated at the node B of the receiver circuit 10, which is then coupled to the node A of the receiver circuit 10 by a gate-to-drain capacitance C2 of the PMOS transistor P2, resulting in a voltage difference ΔVA generated at the node A of the receiver circuit 10. The amount of charges coupled to the node A from the node B of the receiver circuit 10 is represented by Q. The charges Q injected into the node A of the receiver circuit 10 is discharged by a gate-to-drain capacitance C1 of the PMOS transistor P1 until the voltage at the node A is stabilized. ΔVA, ΔVB, and Q can be represented by the following formulae:Q=C2*ΔVB;ΔVA=Q/C1=ΔVB*(C2/C1);ΔVB=VDD−VB;
The charges Q causing the voltage difference ΔVA at the node A of the receiver circuit 10 can be stabilized by the PMOS transistor P1. Since C2 is larger than C1, the receiver circuit 10 has to wait for a long time before and the voltage at the node A becomes stable again. Therefore, the long wait time for the receiver circuit 10 to resume working in the normal mode largely influences the performance of the display device.
FIG. 2 shows a diagram of another prior art receiver circuit 20 of a display device. The receiver circuit 20 differs from the receiver circuit 10 in that the receiver circuit 20 further includes a capacitor Cap coupled between the bias voltage VDD and the node A of the receiver circuit 20. The capacitance of the capacitor Cap is represented by C3. When the receiver circuit 20 exits the power-down mode, a voltage difference ΔVB is generated at the node B of the receiver circuit 20, which is then coupled to the node A of the receiver circuit 20 by a gate-to-drain capacitance C2 of the PMOS transistor P2, resulting in a voltage difference ΔVA′ generated at the node A of the receiver circuit 20. The amount of charges coupled to the node A from the node B of the receiver circuit 20 is represented by Q. The charges Q injected into the node A of the receiver circuit 20 is discharged by a gate-to-drain capacitance C1 of the PMOS transistor P1 and the capacitor Cap until the voltage at the node A is stabilized. ΔVA′, ΔVB, and Q can be represented by the following formulae:Q=C2*ΔVB;ΔVA′=Q/(C1+C3)=ΔVB*C2/(C1+C3);ΔVB=VDD−VB;
With the capacitor Cap, ΔVA′ is smaller than ΔVA, which means the charges Q causing the voltage difference ΔVA′ at the node A of the receiver circuit 20 can be discharged faster. Therefore, the wait time for the receiver circuit 20 to resume working in the normal mode is shorter than that for the receiver circuit 10. However, the capacitor Cap occupies extra space and increases manufacturing cost. Also, the capacitor Cap lengthens the settling time of the receiver circuit 20.